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ACT-SF128K16 High Speed 128Kx16 SRAM/FLASH Multichip Module
CIRCUIT TECHNOLOGY
FEATURES
www.aeroflex.com s Packaging - Hermetic Ceramic
s 2 - 128K x 8 SRAMs & 2 - 128K x 8 Flash Die in
One MCM s Access Times of 25ns (SRAM) and 60ns (Flash) or 35ns (SRAM) and 70 or 90ns (Flash) s 128K x 16 SRAM s 128K x 16 5V Flash s Organized as 128K x 16 of SRAM and 128K x 16 of Flash Memory with Separate Data Buses s Both Blocks of Memory are User Configurable as 256K x 8 s Low Power CMOS s Input and Output TTL Compatible Design s MIL-PRF-38534 Compliant MCMs Available s Decoupling Capacitors and Multiple Grounds for Low Noise s Industrial and Military Temperature Ranges s Industry Standard Pinouts
Note: Programming information available upon request
66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder, Aeroflex code# "P3" q 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7" q 68 Lead, .94" x .94" x .140" Single-Cavity Small Outline Gull Wing, Aeroflex code# "F18" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) s DESC SMD Pending - 5962-96900
q
FLASH MEMORY FEATURES
s Sector Architecture (Each Die)
s s s s s
Equal Sectors of 16K bytes each combination of sectors can be erased with one command sequence. +5V Programing, 5V 10% Supply Embedded Erase and Program Algorithms Hardware and Software Write Protection Internal Program Control Time. 10,000 Erase/Program Cycles
q Any
q8
Block Diagram - PGA Type Package (P3,P7) and CQFP (F18)
Pin Description SWE1 SCE1 SWE2 SCE2 FWE1 FCE1 FWE2 FCE2 FI/O0-15 OE A0 - A16 128Kx8 SRAM 8 SI/O0-7 128Kx8 SRAM 8 SI/O8-15 128Kx8 Flash 8 FI/O0-7 128Kx8 Flash 8 FI/O8-15 SI/O0-15 A0-16 FWE1-2 Flash Data I/O SRAM Data I/O Address Inputs Flash Write Enables
SWE1-2 SRAM Write Enables FCE1-2 SCE1-2 OE NC VCC GND Flash Chip Enables SRAM Chip Enables Output Enable Not Connected Power Supply Ground
eroflex Circuit Technology - Advanced Multichip Modules (c) SCD1677 REV A 4/28/98
Absolute Maximum Ratings
Symbol TC TSTG VG TL Parameter Flash Data Retention Flash Endurance (Write/Erase Cycles) 10 Years 10,000 Rating Case Operating Temperature Storage Temperature Maximum Signal Voltage to Ground Maximum Lead Temperature (10 seconds) Range -55 to +125 -65 to +150 -0.5 to +7 300 Units C C V C
Normal Operating Conditions
Symbol VCC VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Minimum +4.5 +2.2 -0.5 Maximum +5.5 VCC + 0.3 +0.8 Units V V V
Capacitance
(VIN = 0V, f = 1MHz, TC = 25C)
Symbol CAD COE F/S CWE1,2 F/S CCE1,2 F/S CI/O
Parameter A0 - A16 Capacitance OE Capacitance F/S Write Enable Capacitance F/S Chip Enable Capacitance I/O0 - I/O15 Capacitance
Maximum 50 50 20 20 20
Units pF pF pF pF pF
These parameters are guaranteed by design but not tested
DC Characteristics
(VCC = 5.0V, VSS= 0V, TC= -55C to +125C, unless otherwise indicated)
Parameter Input Leakage Current Output Leakage Current
Sym ILI ILO
Conditions VCC = Max, VIN = 0 to VCC FCE = SCE = VIH, OE = VIH, VOUT = 0 to VCC SCE = VIL, OE = VIH, f = 5MHz, VCC = Max, FCE = VIH FCE = SCE = VIH, OE = VIH, f = 5MHz, VCC = Max IOL = 8 mA, VCC = 4.5V IOH = -4.0 mA, , VCC = 4.5V FCE = VIL, OE = VIH, SCE = VIH FCE = VIL, OE = VIH, SCE = VIH IOL = 12 mA, VCC = 4.5V, SCE = VIH
Min
Max Units 10 10 250 40 0.4 A A mA mA V V 100 130 0.45 mA mA V V V
SRAM Operating Supply Current x 16 Mode ICCx16 Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash Vcc Active Current for Read (1) Flash Vcc Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Low Vcc Lock Out Voltage ISB VOL VOH ICC1 ICC2 VOL VOH VLKO
2.4
IOH = -2.5 mA, , VCC = 4.5V, SCE = VIH 0.85 x VCC 3.2
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
SRAM AC Characteristics
(VCC = 5.0V, VSS= 0V, TC = -55C to +125C)
Read Cycle
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Enable to Output Valid Chip Select to Output in Low Z * Output Enable to Output in Low Z * Chip Deselect to Output in High Z * Output Disable to Output in High Z * * Parameters guaranteed by design but not tested Symbol tRC tAA tACE tOH tOE tCLZ tOLZ tCHZ tOHZ 3 0 12 12 0 15 3 0 20 20 -025 Min Max 25 25 25 0 20 -035 Min Max 35 35 35 Units ns ns ns ns ns ns ns ns ns
Write Cycle
Parameter Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Output Active from End of Write * Write to Output in High Z * Data Hold from Write Time Address Hold Time * Parameters guaranteed by design but not tested Symbol tWC tCW tAW tDW tWP tAS tOW tWHZ tDH tAH 0 0 -025 Min Max 25 20 20 15 20 0 0 10 0 0 -035 Min Max 35 25 25 20 25 0 0 20 Units ns ns ns ns ns ns ns ns ns ns
SRAM Truth Table
Mode Standby Read Output Disable Write SCE H L L L OE X L H X SWE X H H L Data I/O High Z Data Out High Z Data In Power Standby Active Active Active
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Timing Diagrams -- SRAM
Read Cycle Timing Diagrams Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
tRC A0-18 tAA tOH DI/O Previous Data Valid Data Valid SCE tAS SWE
SEE NOTE
Write Cycle Timing Diagrams Write Cycle (SWE Controlled, OE = VIH)
tWC A0-18 tAW tCW tAH
tWP
tWHZ
tDW Data Valid
tDW tDH
DI/O
Read Cycle 2 (SWE = VIH)
tRC A0-18 tAA SCE tACE tCLZ
SEE NOTE
Write Cycle (SCE Controlled, OE = VIH )
tWC A0-18 tAW tCHZ
SEE NOTE
tAH tCW
tAS SCE
OE tWP tOE tOLZ
SEE NOTE
tOHZ
SEE NOTE
SWE tDW DI/O Data Valid tDH
DI/O
High Z
Data Valid
UNDEFINED
DON'T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
Current Source IOL
AC Test Conditions
Parameter Typical 0 - 3.0 5 1.5 Units V ns V
To Device Under Test CL = 50 pF
VZ ~ 1.5 V (Bipolar Supply)
Input Pulse Level Input Rise and Fall Input and Output Timing Reference Level
IOH Current Source
Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Flash AC Characteristics - Read Only Operations
(Vcc = 5.0V, Vss = 0V, TC = -55C to +125C)
Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output High Z (1) Output Enable High to Output High Z(1) Output Hold from Address, CE or OE Change, Whichever is First Note 1. Guaranteed by design, but not tested
Symbol -60 -70 -90 Units JEDEC Stand'd Min Max Min Max Min Max
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 60 60 60 30 20 20 0 70 70 70 35 20 20 0 90 90 90 40 25 25 ns ns ns ns ns ns ns
Flash AC Characteristics - Write/Erase/Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55C to +125C)
Parameter
Write Cycle Time Chip Enable Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Enable Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation Sector Erase Time Chip Erase Time Read Recovery Time before Write Vcc Setup Time Output Enable Setup Time Output Enable Hold Time1 Note: 1. For Toggle and Data Polling.
Symbol JEDEC Stand'd
tAVAC tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHEH tWHWL tWHWH1 tWHWH2 tWHWH3 tGHWL tVCE tOES tOEH tWC tCE tWP tAS tDS tDH tAH tCH tWPH
-60 -70 -90 Min Max Min Max Min Max
60 0 30 0 30 0 45 0 20 14 TYP 60 120 0 50 12.5 10 10 0 50 12.5 10 70 0 35 0 30 0 45 0 20 14 TYP 60 120 0 50 12.5 90 0 45 0 45 0 45 0 20 14 TYP 60 120
Units
ns ns ns ns ns ns ns ns ns s Sec Sec s s Sec ns
Flash AC Characteristics - Write/Erase/Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55C to +125C)
Parameter
Write Cycle Time Write Enable Setup Time Chip Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Hold from Write Enable High Chip Enable Pulse Width High Duration of Byte Programming Sector Erase Time Chip Erase Time Read Recovery Time Chip Programming Time
Symbol JEDEC Stand'd
tAVAC tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHWH tEHEL tWHWH1 tWHWH2 tWHWH3 tWC tWS tCP tAS tDS tDH tAH tWH tCPH
-60 -70 -90 Min Max Min Max Min Max
60 0 35 0 30 0 45 0 20 14 TYP 60 120 0 12.5 0 12.5 70 0 35 0 30 0 45 0 20 14 TYP 60 120 0 12.5 90 0 50 0 50 0 50 0 20 14 TYP 60 120
Units
ns ns ns ns ns ns ns ns ns s Sec Sec ns Sec
tGHEL
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
AC Waveforms for Flash Memory Read Operations
tRC
Addresses Addresses Stable
tACC
FCE
tDF
OE
tOE
FWE
tCE
Outputs High Z
tOH
Output Valid High Z
Write/Erase/Program Operation for Flash Memory, FWE Controlled
Data Polling Addresses 5555H tWC FCE tGHWL OE tWP FWE tCE tDH AOH Data tDS PD D7 DOUT tOH tOE tWPH tDF tWHWH1 tAS PA tAH PA tRC
5.0V tCE
Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
AC Waveforms Chip/Sector Erase Operations for Flash Memory
tAS Addresses 5555H tAH 2AAAH Data Polling 5555H 5555H 2AAAH SA
FCE tGHWL OE tWP FWE tCE Data tWPH tDH AAH tDS VCC 55H 80H AAH 55H 10H/30H
tVCE
Notes: 1. SA is the sector address for sector erase.
AC Waveforms for Data Polling During Embedded Algorithm Operations for Flash Memory
tCH
FCE
tDF tOE
OE
tOEH
FWE
tCE tOH *
DQ7 DQ7 DQ7= Valid Data High Z
tWHWH1 or 2
DQ0-DQ6 DQ0-DQ6=Invalid
DQ0-DQ6 Valid Data
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Write/Erase/Program Operation for Flash Memory, FCE Controlled
Data Polling Addresses 5555H tWC FWE tGHWL OE tCP FCE tWS tCPH tDH AOH Data tDS PD D7 DOUT tWHWH1 tAS PA tAH PA
5.0V
Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Pin Numbers & Functions
66 Pins -- PGA-Type
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function SI/O8 SI/O9 SI/O10 A13 A14 A15 A16 NC SI/O0 SI/O1 SI/O2 SWE2 SCE2 GND SI/O11 A10 A11 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function A12 Vcc SCE1 NC SI/O3 SI/O15 SI/O14 SI/O13 SI/O12 OE NC SWE1 SI/O7 SI/O6 SI/O5 SI/O4 FI/O8 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function FI/O9 FI/O10 A6 A7 NC A8 A9 FI/O0 FI/O1 FI/O2 VCC FCE2 FWE2 FI/O11 A3 A4 A5 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Function FWE1 FCE1 GND FI/O3 FI/O15 FI/O14 FI/O13 FI/O12 A0 A1 A2 FI/O7 FI/O6 FI/O5 FI/O4
"P3" -- 1.08" SQ PGA Type (without shoulder) Package "P7" -- 1.08" SQ PGA Type (with shoulder) Package Bottom View (P7 & P3) Side View (P7)
.185 MAX .025 .035 .050 Pin 56
Side View (P3)
1.085 SQ MAX 1.000 .600 Pin 1
1.030 1.040
.100
1.030 1.040
.100
1.000
.020 .016 .180 TYP
.020 .016 Pin 66 Pin 11 .180 TYP .160 MAX .100
All dimensions in inches
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Pin Numbers & Functions
68 Pins -- Dual-Cavity CQFP
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function GND FCE1 A5 A4 A3 A2 A1 A0 NC SI/O0 SI/O1 SI/O2 SI/O3 SI/O4 SI/O5 SI/O6 SI/O7 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function GND SI/O8 SI/O9 SI/O10 SI/O11 SI/O12 SI/O13 SI/O14 SI/O15 Vcc A11 A12 A13 A14 A15 A16 SCE1 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function OE SCE2 NC SWE2 FWE1 FWE2 NC NC NC FI/O15 FI/O14 FI/O13 FI/O12 FI/O11 FI/O10 FI/O9 FI/O8 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function GND FI/O7 FI/O6 FI/O5 FI/O4 FI/O3 FI/O2 FI/O1 FI/O0 VCC A10 A9 A8 A7 A6 SWE1 FCE2
"F18" -- CQFP Package
.990 SQ .010 .940 SQ .010 .140 MAX Pin 61 Pin 60 .008 .002 .040 .015 .002 .900 SQ REF .640 SQ REF Metal spacer .010 .008 .015 .002
Pin 9 Pin 10
Detail "A"
Pin 26 Pin 27 .800 REF
Pin 44 Pin 43 See Detail "A"
All dimensions in inches
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
ACT-SF128K16N -26P3Q ACT-SF128K16N -37P3Q ACT-SF128K16N -39P3Q ACT-SF128K16N -26P7Q ACT-SF128K16N -37P7Q ACT-SF128K16N -39P7Q ACT-SF128K16N -26F18Q ACT-SF128K16N -37F18Q ACT-SF128K16N -39F18Q
Note: (S) = Speed for SRAM, (F) = Speed for FLASH * Pending
DESC SMD Number
5462-96900* 5462-96900* 5462-96900* 5462-96900* 5462-96900* 5462-96900* 5462-96900* 5462-96900* 5462-96900*
Speed
25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns 25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns 25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns
Package
1.08"SQ PGA-Type 1.08"SQ PGA-Type 1.08"SQ PGA-Type 1.08"SQ PGA-Type 1.08"SQ PGA-Type 1.08"SQ PGA-Type .94"sq CQFP .94"sq CQFP .94"sq CQFP
Part Number Breakdown
ACT- S F 128K 16 N- 26 P7 Q
Aeroflex Circuit Technology Memory Type S (SRAM) & F (FLASH) Combo Memory Depth Options, N = none Memory Width, Bits Memory Speed cODE 26 = 25ns SRAM & 60ns FLASH 37 = 35ns SRAM & 70ns FLASH 39 = 35ns SRAM & 90ns FLASH Screening C = Commercial Temp, 0C to +70C I = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C, Screening * Q = MIL-PRF-38534 Compliant / SMD Package Type & Size Surface Mount Packages Thru-Hole Packages F18 = .94"SQ 68 Lead Dual-Cavity P3 = 1.085"SQ PGA 66 Pins with out shoulder CQFP P7 = 1.085"SQ PGA 66 Pins with shoulder
* Screened to the individual test methods of MIL-STD-883
Specification subject to change without notice
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830
Aeroflex Circuit Technology
Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553
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SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700

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